As processors in computers and other electronic systems continue to operate at ever higher speeds, demands have been placed on memory devices to keep up. As a result, current memory device designs have sought to increase their effective transfer rates on memory buses by providing memory interfaces with burst transfers of data at ever increasing clock rates. However, although it has been possible to increase the transfer rates of memory buses, it has not proven to be so easy to increase the speed of the memory cells within the memory devices, themselves. For read operations, a common answer to this situation is for a memory device to internally prefetch ever greater quantities of data from an open row of memory cells at a time to support burst transfers of data of ever greater quantities of data to minimize proportion of bus cycles used in transferring addresses and/or commands versus transferring data.
Unfortunately, increasing the quantity of data prefetched and the burst length is not necessarily optimal for the architectures of every electronic system, especially computer systems employed as a servers where processors frequently jump about between many different pieces of software and/or pieces of data to support a given piece of software as a result of the demands arising from the many users that servers must typically support at any given time. For servers, this results in a pattern of operation of loading, executing and storing only a small portion of software instructions and/or data at a time before jumping to loading, executing and storing another small portion of software instructions and/or data, likely resulting in far more jumping about between different locations in memory devices to read and write what are likely smaller quantities of bytes than the quantities of bytes that current memory devices are designed to transfer in a burst. In other electronic systems, such as a single-user computer (e.g., a desktop computer, notebook computer, handheld computer, etc.) increased burst length is more likely to be helpful since, generally speaking, the user of such a single-user computer does not usually choose to work with so many different pieces of software and/or data at any given time, and so jumping around between different locations within a memory device occurs less frequently. So, the general tendency of such single-user computers is to execute a greater number of instructions between jumps than servers, tending to cause more of the quantities of data prefetched from a row of memory cells and transferred in burst transfers by current memory devices to actually be used.
Another factor aggravating the problem of excessive quantities of bytes being prefetched and transferred in burst transfers for servers arises from the expectation that servers meet standards of reliability and immunity to hardware errors that single-user computers don't. Memory systems in servers often require wider memory buses (or multiple memory buses operated in parallel to achieve the equivalent of a single wider memory bus) to increase the number of bits transferred during a given clock cycle to support any of a number of possible schemes for error detection, error correction, error scrubbing, chipkill, etc. Unfortunately, this use of wider (or multiple parallel) memory bus configurations actually multiplies the already excessive quantities of data prefetched and transferred in burst transfers, usually by a factor of two or four.
The fact that single-user computers vastly outnumber servers gives rise to a tendency for memory devices to be designed with design trade-offs that are often made more in favor of single-user computers than for servers. The result is the preservation of the approach of prefetching and transferring large quantities of data, and even where the ability is provided in some current memory devices to program a memory device to specify a smaller quantity of data to be prefetched and transferred, limits are typically placed on how small a quantity can be specified. However, in one effort to accommodate the growing disparity between increasing quantities of data prefetched and transferred in a burst versus the quantities of data actually needed, some current memory devices provide the ability to selectively bring about an early termination of a burst transfer so as to limit the number of bytes transferred in a burst with a “burst terminate” command, a “burst chop” command embedded in a read command, etc. Unfortunately, the use of a burst terminate command takes up memory bus cycles to transmit the command, and the command must be timed to be transmitted either during or just before the clock cycle during which the last desired byte(s) are transferred, which may also momentarily preclude the use of a memory bus for other transfers. Regardless of how a memory device is instructed to terminate a burst, early, a delay is still incurred (causing valuable memory bus cycles to pass, unused—i.e., “dead time” on a memory bus) to allow a memory device designed to prefetch a large quantity of data to discontinue prefetching an amount of unwanted data, and to become ready to carry out another memory operation. Given that processors used in both typical servers and single-user computers tend to have cache systems with cache rows of only a few quadwords in width, server computer systems are currently more likely to frequently use mechanisms to terminate burst transfers, early. However, as the disparity between memory bus speeds and memory cell speeds continues to increase, it is expected that the disparity between quantities of data prefetched and transferred in complete burst transfers will increase, and it is expected that even single-user computers will start making frequent use of mechanisms to terminate burst transfers, early.